diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index de3ea00..fc92cd8 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -66,20 +66,20 @@
 #endif
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #ifdef CONFIG_PCIE1
-	SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
 #else /* !CONFIG_PCIE1 */
-	SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
-	SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
 #ifdef CONFIG_PCIE1
-	SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
 #endif /* CONFIG_PCIE */
 };
 
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index 9c5c12c..dea652d 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -41,10 +41,10 @@
 extern uint get_lbc_clock (void);
 
 /* index of UPM RAM array run pattern for NAND command cycle */
-#define	CFG_NAN_UPM_WRITE_CMD_OFS	0x08
+#define	CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS	0x08
 
 /* index of UPM RAM array run pattern for NAND address cycle */
-#define	CFG_NAND_UPM_WRITE_ADDR_OFS	0x10
+#define	CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x10
 
 /* Structure for table with supported UPM timings */
 struct upm_freq {
@@ -377,7 +377,7 @@
  */
 static void upmb_write (u_char addr, ulong val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	out_be32 (&lbc->mdr, val);
 
@@ -385,7 +385,7 @@
 			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 
 	/* dummy access to perform write */
-	out_8 ((void __iomem *)CFG_NAND0_BASE, 0);
+	out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0);
 
 	clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
 }
@@ -396,11 +396,11 @@
 static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
 {
 	uint i;
-	uint or3 = CFG_OR3_PRELIM;
+	uint or3 = CONFIG_SYS_OR3_PRELIM;
 	uint clock = get_lbc_clock ();
 
 	out_be32 (&lbc->br3, 0);	/* disable bank and reset all bits */
-	out_be32 (&lbc->br3, CFG_BR3_PRELIM);
+	out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
 
 	/*
 	 * Search appropriate UPM table for bus clock.
@@ -455,7 +455,7 @@
 
 int board_nand_init (struct nand_chip *nand)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	if (!nand_upm_patt)
 		nand_upm_setup (lbc);
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 33bc407..783b280 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -66,9 +66,9 @@
 long int sdram_setup (int casl)
 {
 	int i;
-	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 #ifdef CONFIG_TQM8548
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #else /* !CONFIG_TQM8548 */
 	unsigned long cfg_ddr_timing1;
 	unsigned long cfg_ddr_mode;
@@ -296,7 +296,7 @@
 	 * This DLL-Override only used on TQM8540 and TQM8560
 	 */
 	{
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 		int i, x;
 
 		x = 10;
@@ -336,11 +336,11 @@
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf ("SDRAM test phase 1:\n");
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 380448a..16b102d 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -28,19 +28,19 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
-		       CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
-		       CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
-		       CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -50,11 +50,11 @@
 	 * 0xf8000000	128M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 1, BOOKE_PAGESZ_64M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
-		       CFG_FLASH_BASE + 0x4000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+		       CONFIG_SYS_FLASH_BASE + 0x4000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 0, BOOKE_PAGESZ_64M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,8 +70,8 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
-		       CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -80,7 +80,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	PCI express MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,8 +88,8 @@
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	PCI express MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
-		       CFG_PCIE1_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
+		       CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
@@ -97,7 +97,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -105,8 +105,8 @@
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
-		       CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		       CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 #endif /* CONFIG_PCIE */
@@ -117,7 +117,7 @@
 	 * 0xe2000000	 16M	PCI1 IO
 	 * 0xe3000000	 16M	CAN and NAND Flash
 	 */
-	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -128,12 +128,12 @@
 	 * Make sure the TLB count at the top of this table is correct.
 	 * Likely it needs to be increased by two for these entries.
 	 */
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 7, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
-		       CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 8, BOOKE_PAGESZ_256M, 1),
 
@@ -142,7 +142,7 @@
 	 * TLB 9:	 16M	Non-cacheable, guarded
 	 * 0xef000000	 16M	PCI express IO
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 9, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
@@ -154,19 +154,19 @@
 	 * 0xc0000000	  1G	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 3, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
-		       CFG_FLASH_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
+		       CONFIG_SYS_FLASH_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 2, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
-		       CFG_FLASH_BASE + 0x20000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
+		       CONFIG_SYS_FLASH_BASE + 0x20000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 1, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
-		       CFG_FLASH_BASE + 0x30000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
+		       CONFIG_SYS_FLASH_BASE + 0x30000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 0, BOOKE_PAGESZ_256M, 1),
 
@@ -174,7 +174,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -182,8 +182,8 @@
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
-		       CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 
@@ -192,7 +192,7 @@
 	 * TLB 6:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	PCI express MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
@@ -200,7 +200,7 @@
 	 * TLB 6:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_256M, 1),
 
@@ -212,7 +212,7 @@
 	 * 0xa2000000	 16M	PCI1 IO
 	 * 0xa3000000	 16M	CAN and NAND Flash
 	 */
-	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 7, BOOKE_PAGESZ_64M, 1),
 
@@ -223,12 +223,12 @@
 	 * Make sure the TLB count at the top of this table is correct.
 	 * Likely it needs to be increased by two for these entries.
 	 */
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 8, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
-		       CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 9, BOOKE_PAGESZ_256M, 1),
 
@@ -237,7 +237,7 @@
 	 * TLB 10:	 16M	Non-cacheable, guarded
 	 * 0xaf000000	 16M	PCI express IO
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 10, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 5314d33..f69de95 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -269,7 +269,7 @@
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	/*
 	 * Adjust flash start and offset to detected values
@@ -282,9 +282,9 @@
 	 */
 	if (flash_info[0].size > 0) {
 		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
-			(CFG_OR1_PRELIM & 0x00007fff);
+			(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
 		memctl->br1 = gd->bd->bi_flashstart |
-			(CFG_BR1_PRELIM & 0x00007fff);
+			(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
 		/*
 		 * Re-check to get correct base address for bank 1
 		 */
@@ -298,9 +298,9 @@
 	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
 	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
-		(CFG_OR0_PRELIM & 0x00007fff);
+		(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
 	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
-		(CFG_BR0_PRELIM & 0x00007fff);
+		(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
 	/*
 	 * Re-check to get correct base address for bank 0
 	 */
@@ -311,26 +311,26 @@
 	 */
 	flash_protect (FLAG_PROTECT_CLEAR,
 		       gd->bd->bi_flashstart, 0xffffffff,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Environment protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_ENV_ADDR,
 		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 #ifdef CONFIG_ENV_ADDR_REDUND
 	/* Redundant environment protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_ENV_ADDR_REDUND,
 		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 #endif
 
 	return 0;
@@ -342,7 +342,7 @@
  */
 static void upmc_write (u_char addr, uint val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	out_be32 (&lbc->mdr, val);
 
@@ -350,7 +350,7 @@
 			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 
 	/* dummy access to perform write */
-	out_8 ((void __iomem *)CFG_CAN_BASE, 0);
+	out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
 
 	/* normal operation */
 	clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
@@ -359,7 +359,7 @@
 
 uint get_lbc_clock (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	sys_info_t sys_info;
 	ulong clkdiv = lbc->lcrr & 0x0f;
 
@@ -376,7 +376,7 @@
 		return sys_info.freqSystemBus / clkdiv;
 	}
 
-	puts("Invalid clock divider value in CFG_LBC_LCRR\n");
+	puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
 
 	return 0;
 }
@@ -386,8 +386,8 @@
  */
 void local_bus_init (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint lbc_mhz = get_lbc_clock ()  / 1000000;
 
 #ifdef CONFIG_MPC8548
@@ -418,7 +418,7 @@
 		gur->lbiuiplldcr1 = dummy;
 	}
 
-	lcrr = CFG_LBC_LCRR;
+	lcrr = CONFIG_SYS_LBC_LCRR;
 
 	/*
 	 * Local Bus Clock > 83.3 MHz. According to timing
@@ -464,12 +464,12 @@
 	 */
 
 	if (lbc_mhz < 66) {
-		lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
 		lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
 			     LTEDR_RAWA | LTEDR_CSD;	/* Disable all error checking */
 
 	} else if (lbc_mhz >= 133) {
-		lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
 
 	} else {
 		/*
@@ -484,7 +484,7 @@
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
 		udelay (200);
 
 		/*
@@ -503,10 +503,10 @@
 	 * set if Local Bus Clock is > 83 MHz.
 	 */
 	if (lbc_mhz > 83)
-		out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
+		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
 	else
-		out_be32 (&lbc->or2, CFG_OR2_CAN);
-	out_be32 (&lbc->br2, CFG_BR2_CAN);
+		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
+	out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
 
 	/* LGPL4 is UPWAIT */
 	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
@@ -548,10 +548,10 @@
 
 static inline void init_pci1(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 
@@ -579,24 +579,24 @@
 
 		/* inbound */
 		pci_set_region (hose->regions + 0,
-				CFG_PCI_MEMORY_BUS,
-				CFG_PCI_MEMORY_PHYS,
-				CFG_PCI_MEMORY_SIZE,
+				CONFIG_SYS_PCI_MEMORY_BUS,
+				CONFIG_SYS_PCI_MEMORY_PHYS,
+				CONFIG_SYS_PCI_MEMORY_SIZE,
 				PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 
 		/* outbound memory */
 		pci_set_region (hose->regions + 1,
-				CFG_PCI1_MEM_BASE,
-				CFG_PCI1_MEM_PHYS,
-				CFG_PCI1_MEM_SIZE,
+				CONFIG_SYS_PCI1_MEM_BASE,
+				CONFIG_SYS_PCI1_MEM_PHYS,
+				CONFIG_SYS_PCI1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region (hose->regions + 2,
-				CFG_PCI1_IO_BASE,
-				CFG_PCI1_IO_PHYS,
-				CFG_PCI1_IO_SIZE,
+				CONFIG_SYS_PCI1_IO_BASE,
+				CONFIG_SYS_PCI1_IO_PHYS,
+				CONFIG_SYS_PCI1_IO_SIZE,
 				PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -636,11 +636,11 @@
 
 static inline void init_pcie1(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_PCIE1
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) ||
@@ -661,23 +661,23 @@
 
 		/* inbound */
 		pci_set_region (hose->regions + 0,
-				CFG_PCI_MEMORY_BUS,
-				CFG_PCI_MEMORY_PHYS,
-				CFG_PCI_MEMORY_SIZE,
+				CONFIG_SYS_PCI_MEMORY_BUS,
+				CONFIG_SYS_PCI_MEMORY_PHYS,
+				CONFIG_SYS_PCI_MEMORY_SIZE,
 				PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region (hose->regions + 1,
-				CFG_PCIE1_MEM_BASE,
-				CFG_PCIE1_MEM_PHYS,
-				CFG_PCIE1_MEM_SIZE,
+				CONFIG_SYS_PCIE1_MEM_BASE,
+				CONFIG_SYS_PCIE1_MEM_PHYS,
+				CONFIG_SYS_PCIE1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region (hose->regions + 2,
-				CFG_PCIE1_IO_BASE,
-				CFG_PCIE1_IO_PHYS,
-				CFG_PCIE1_IO_SIZE,
+				CONFIG_SYS_PCIE1_IO_BASE,
+				CONFIG_SYS_PCIE1_IO_PHYS,
+				CONFIG_SYS_PCIE1_IO_SIZE,
 				PCI_REGION_IO);
 
 		hose->region_count = 3;